In the production process of semiconductor integrated circuit devices, after a great number of integrated circuits are formed on a wafer, a probe test is generally conducted as to each of these integrated circuits. This wafer is then cut, thereby forming semiconductor chips. Such semiconductor chips are contained and sealed in respective proper packages. Each of the packaged semiconductor integrated circuit devices is further subjected to a burn-in test. In order to give a quality certification to a semiconductor integrated circuit device, it is extremely important to not only inspect electrical properties of the semiconductor integrated circuit device, but also inspect electrical properties of the semiconductor chip itself by the burn-in test. Besides, in recent years, there has been developed a mounting method that a semiconductor chip itself is used as an integrated circuit device to directly mount a circuit device composed of the semiconductor chip on, for example, a printed circuit board. Therefore, there is a demand for guaranteeing the quality of the semiconductor chip itself.
Since the semiconductor chip is minute, and its handling is inconvenient, however, it takes a long time to conduct the inspection of the circuit device composed of the semiconductor chip, and inspection cost thus becomes considerably high.
From such reasons, attention has been recently paid to a WLBI (Wafer Level Burn-in) test in which the electrical properties of a circuit device composed of a semiconductor chip are inspected in the state of a wafer.
On the other hand, in the probe test conducted on integrated circuits formed on a wafer, a method, in which a probe test is collectively performed on, for example, 16 or 32 integrated circuits among a great number of integrated circuits formed on a wafer, and the probe test is successively performed on other integrated circuits, is generally adopted.
However, in recent years, there has been a demand for collectively performing a probe test on, for example, 64 or 124 integrated circuits, or all integrated circuits among a great number of integrated circuits formed on a wafer for the purpose of improving inspection efficiency and reducing inspection cost.
FIG. 17 is a cross-sectional view schematically illustrating the construction of an exemplary conventional wafer inspection apparatus for conducting the WLBI test or probe test as to a wafer on which a great number of integrated circuits have been formed. Such wafer inspection apparatus are described in, for example, Patent Art. 1 and Patent Art. 2.
This wafer inspection apparatus has a circuit board 80 for inspection, on the front surface (lower surface in FIG. 17) of which a great number of inspection electrodes 81 have been formed, and a probe card 90 is arranged on the front surface of the circuit board 80 for inspection through a connector 85. This probe card 90 is constructed by a circuit board 91 for connection and a contact member 95 provided on the front surface (lower surface in FIG. 17) of the circuit board 91 for connection and having a great number of contacts (not illustrated) brought into contact with electrodes (not illustrated) to be inspected of integrated circuits in a wafer W that is an object of inspection. A wafer tray 96 which also serves as a heating plate, on which the wafer W that is the object of inspection is mounted, is arranged under the contact member 95.
Here, as the contact member 95, may be used that composed of an anisotropically conductive sheet, in which the contacts are composed of a plurality of conductive parts for connection each extending in a thickness-wise direction of the sheet have been mutually insulated by an insulating part, that composed of a sheet-like connector, in which contacts each composed of a metallic body and extending through an insulating sheet in a thickness-wise direction thereof have been arranged in the insulating sheet, that obtained by laminating an anisotropically conductive sheet and a sheet-like connector, or the like.
On a back surface of the circuit board 91 for connection in the probe card 90, a great number of terminal electrodes 92 are formed in accordance with a pattern corresponding to a pattern of the inspection electrodes 81 of the circuit board 80 for inspection, and the circuit board 91 for connection is arranged in such a manner that the terminal electrodes 92 are respectively opposed to the inspection electrodes 81 of the circuit board 80 for inspection by guide pins 93.
In the connector 85, a great number of connecting pins 86 called “pogo pins”, which can be elastically compressed in a lengthwise direction thereof are arranged in accordance with the pattern corresponding to the pattern of the inspection electrodes 81 of the circuit board 80 for inspection. The connector 85 is arranged in a state that the connecting pins 86 have been respectively located between the inspection electrodes 81 of the circuit board 80 for inspection and the terminal electrodes 92 of the circuit board 91 for connection.
In this wafer inspection apparatus, the wafer W that is the object of inspection is mounted on the wafer tray 96, and the wafer tray 96 is moved upward by a suitable drive means (not illustrated), whereby the wafer W is brought into contact with the probe card 90. By being further pressurized upward from this state, each of the connecting pins 86 of the connector 85 is elastically compressed in a longitudinal direction thereof, whereby the respective inspection electrodes 81 of the circuit board 80 for inspection are electrically connected to the respective terminal electrodes 92 of the circuit board 91 for connection, and the respective contacts of the contact member 95 come into contact with the respective electrodes to be inspected of a part of the integrated circuits formed on the wafer W, thereby achieving necessary electrical connection. The wafer W is then heated to a predetermined temperature by the wafer tray 96 to perform necessary electrical inspection (WLBI test or probe test) as to the wafer W in this state.
Patent Art. 1: Japanese Patent Application Laid-Open No. 2000-147063;
Patent Art. 2: Japanese Patent Application Laid-Open No. 2000-323535